Google and Facebook should proceed with an update of their servers at the end of the year which will coincide with the release of the Interlagos of AMD and the Romley, the new Sandy Bridge for Intel Server using a Socket LGA 2011. According to DigiTimes, who allegedly received information from manufacturers of servers, this should create a wave of renewal of machines and related products, such as storage or network devices.
Romley will integrate eight cores taking processors support Hyper-Threading and motherboards dual for a maximum of 32 threads. Companies are now restored the economic crisis according to assemblers, which are cited by DigiTimes. Their new economic health explains this desire to update their infrastructure.
Intel showed the first Romley to the IDF in September 2010. They integrate a memory controller channel compatible DDR3 LRDIMM (Load Reduced Dual-Inline Memory Modules) that allows systems using more than 32 GB of memory to turn each bar to its maximum rate. Conventional controllers are unable to maintain the integrity of the data of this type of configuration because of a deterioration of the signal that occurs when using all chip memory. With the LRDIMM, Intel can support 96 GB without loss of frequency.
The LRDIMM uses a buffer which reduces the flow of information between the processor and memory. The bus is therefore less taxed by the increase in the memory modules. The LRDIMM is a derivative of the MetaRAM technology. It allows to virtually consolidate a series of memory chips to simplify the task of the controller and increase the capacity of the bar. For example, it is possible to place 32 125 MB modules for a bar of 4 GB and the system sees that 500 MB 8 chips. It can be more modules on a bar. The problem is that the buffer required for the proper functioning of this technology is expensive, which explains that the LRDIMM are before any reserved for servers.
Rumours that circulated last month the Sandy Bridge Romley will use memory cache L3 2.5 MB per core, for a total of 20 MB, and will have a TDP which will be included between 40 W and 95 W following the requests of the system. They will be coupled with the chipset Intel Patsburg-B. The Romley should be marketed under the name of Xeon E5. They will also have two links QPI, 40 rows PCI-Express 3.0, 4 DMI 2.0.
They will be opposed to the Interlagos of AMD will be built on the Bulldozer architecture. They integrate between twelve and sixteen cores, memory four channels and 16 MB of L3 cache controller. They should be marketed at the same time as the Romley.
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