PCI-Express x 2 for Intel?

Intel, according to our colleagues, would like the PCI-Express x 2 democratizes and is actually available, whereas only x 1, x 4, x 8 and x 16 connectors are standardized. Indeed, the standard allows in theory also use x 2, x 12 and x 32, even if no one uses.Intel problem is linked to its chipsets: whether on Atom or Core ix, the number of PCI-Express lines available is low. On Atom, there are 4 PCI-Express lines at 250 MB/s, on the other chipsets, it was either 8 lines at 250 MB/s (series 5) or 8 lines at 500 MB/s (series 6). And the whole is therefore little flexible: for devices that need bandwidth, there is for example not solutions on Atom, because it is impossible to reserve 4 lines for a single controller, other devices (such as Wi - Fi) in need of a line. And even on platforms above range, be forced to book 4 lines for a controller is a problem.

In fact, the absence of PCI-Express x 2 problems: either controllers are underexploited as connected USB 3.0 chips on the PCI-Express x 1 to 250 MB/s, or there is an additional cost to solve the problem. Indeed, some manufacturers use chips that will aggregate two PCI-Express lines at 250 MB/s to get a single 500 MB/s, for example. For SATA 6 GB/s controllers, should be ideally two lines at 500 MB/S and 4 lines are not needed.

Remains that for the moment there is no is standardized and PCI-Express 3.0 (which runs to 1 GB/s line) and the integration of some functions in the chipset (such as USB 3.0) will reduce the magnitude of the problem. Pending the next standard request bandwidth.