IBM Racetrack memory could be a reality by 2020

Une piste de Racetrack


IBM gave a Conference of press last Wednesday on his memories of the future and for the first time, Big Blue States that its Racetack could be a reality by the end of the Decade. In addition, by three years of capacity of 1 Po can be stored in a surface equal to a 1U rack, always according to the firm.


We presented you the progress of the IBM's Racetrack last December. A reminder, this memory is based on a mechanism different from the current submissions. Instead of fetching the data bit in the cell, as is the case today, it moves on a track of a few tens of nanometers in thickness. Researchers still need many challenges and better understand its functioning, but published last December results allow to consider marketing in five to seven years, according to Big Blue. We are nevertheless talking about a project that could be abandoned or used for other purposes.


La Millipede d'IBM


This is not the first time that IBM would work on a memory that would not see the day. Is remembered for his research on the Millepede, a chip where the information is stored in holes etched in a fine polymer. The memory cells are written and read by one of the multiple branches of a MEMS walks on the surface. The Millipede was scheduled for 2007, but too high production costs were ultimately correct its existence. The technology is not dead. Gerd Bining, head of the project at IBM, said during the Conference IEEE last May that the firm was still working on it, but no more account do the memory of tomorrow. Big Blue recycle technologies developed in other products, such as probes used in lithographic processes.


During the Conference last Wednesday, IBM has also pledged to increase memory density, without giving more details. He spoke only of "magnetic technology", according to IDG that reported the event. The fact that this technology arrives within three years suggests that he is working on his own MRAM, which would be nothing surprising. We know that it has partnered with TDK to his development and he presented a paper at the IEDM (International Electron Device Meeting) in 2010 (see "IBM and Samsung talk TWU RAM").


Things change very quickly and the STT-MRAM could start to compete with Flash memory within three years (cf. "Toshiba would out a STT-MRAM in 3 years"). Research in this area abound (cf. "A new structure of MRAM") and manufacturers show more enthusiasm for this technology, which is always a good sign.


For the record, the STT-MRAM is based on spin transfer torque (Spin-Transfer Torque in English) which is a phenomenon appearing when a spin-polarised current (which contains electrons with the same angular movement, Editor's note) passes through the junction magnetic tunnel, a structure composed of two ferromagnetic elements separated by a thin insulating layer. As shown in the diagram on the left, one of the ferromagnetic layers is said trapped by Antiferromagnetic element. Whatever happens, its polarity will remain unchanged. However, the other layer is free and the polarized current through the junction tunnel effect, it will adopt the spin of electron sent, a phenomenon known as Spin-transfer Switching. We will then measure the magnetic strength of the structure. If it is strong, it means that the two ferromagnetic plates have opposite polarities, which represents a 0. If it is low, the polarities are identical, which is a 1.

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